A conventional high-speed interface circuit is formed of a receiver circuit (RX) that receives external data and performs serial-parallel conversion thereof, a transmitter circuit (TX) that performs parallel-serial conversion of internal data, and a PLL that multiplies an external reference clock and supplies it to the RX and TX. In an apparatus comprising multiple channels constituted such that an RX is coupled with a TX, one PLL generally supplies a clock commonly to the multiple channels. However, in this case, the data speed cannot be changed for each channel. It is thought to be possible to change the data speed by frequency-dividing the clock with a frequency divider circuit, however, it is difficult to realize this when the data speed ratio is not an integer.
A circuit shown in FIG. 5 is known as a fractional frequency divider circuit where the N of its frequency division ratio (1/N) is not an integer. (Refer to Patent Document 1.) The fractional frequency divider circuit shown in FIG. 5 uses adders et al., therefore the circuit scale becomes large. Furthermore, it is constituted such that it obtains a desired fraction frequency-divided output by varying the frequency division ratio over time and obtaining the average, therefore, it cannot be used at all as a clock to be supplied to an RX and a TX that require a waveform with a duty ratio of 50%. For this reason, conventionally a PLL is provided for each channel as shown in FIG. 6a, or two PLLs are shared by multiple channels as shown in FIG. 6b. 
[Patent Document 1]
Japanese Patent Kokai Publication No. JP-P2001-251181A (FIG. 1)